The present invention relates to relaxation oscillators, and, more particularly, to relaxation oscillators with low power consumption.
Relaxation oscillators are widely used in modern electronic systems such as radio, telecommunications, computers, and other electronic systems for the generation of oscillator signals. Oscillator signals are required to meet timing critical requirements such as modulation and demodulation of message signals in communication systems, synchronous operation of electronic circuits, and so forth. A relaxation oscillator includes a resistor-capacitor (RC) circuit. An oscillator signal is generated by charging and discharging the capacitor through the RC circuit. The frequency of the oscillator signal is varied by varying the time constant of the RC circuit. For example, to increase the frequency of the oscillator signal, the value of the resistor can be reduced. However, this results in higher power consumption.
Referring to FIG. 1A, a schematic diagram illustrating a conventional relaxation oscillator 100 is shown. The conventional relaxation oscillator 100 includes a ramp voltage generating circuit 102, a reference voltage generating circuit 104, a switching signal generating circuit 106, and an oscillator signal generating circuit 108. The ramp voltage generating circuit 102 includes a charging resistor 110 (Rcharge) and capacitors 112a and 112b (C1 and C2 respectively). The reference voltage generating circuit 104 includes resistors 114a and 114b (R1 and R2 respectively). The switching signal generating circuit 106 includes comparators 116a and 116b, an AND gate 118, and a divide-by-2 counter 120. The oscillator signal generating circuit 108 includes NOT gates 122a and 122b. 
The charging resistor 110 is connected to a voltage source VDD. The capacitor 112a is connected between the charging resistor 110 and ground. More particularly, one terminal of the capacitor 112a is connected to the charging resistor 110 through a switch D2 and the other terminal is connected to ground. A switch S1 is connected in parallel with the capacitor 112a. Charging of the capacitor 112a is initiated by closing switch D2 and keeping switch S1 open. The capacitor 112a is discharged by closing switch S1 and opening switch D2. The capacitor 112b is connected between the charging resistor 110 and ground in a configuration similar to that of the capacitor 112a with switches D1 and S2, which are used to charge and discharge the capacitor 112b. 
The capacitors 112a and 112b also are connected to the negative terminals of the comparators 116a and 116b, respectively. The positive terminals of the comparators 116a and 116b are connected to the reference voltage generating circuit 104 at a voltage tap T1. The resistors 114a and 114b of the voltage generating circuit 104 are connected in series between the voltage source VDD and ground with the voltage tap T1 being located at a node between the resistors 114a, 114b. 
The output terminals of the comparators 116a and 116b are connected to the input terminals of the AND gate 118. The output of the AND gate 118 is connected to the divide-by-2 counter 120. The outputs of the divide-by-2 counter 120 are ramp voltage switching signals D1′ and D2′, which are provided to the ramp voltage generating circuit 102 to control switches S1, D1 and S2, D2 respectively. The ramp voltage switching signal D2′ is the complement of the ramp voltage switching signal D1′.
Referring now to FIG. 1B, a timing diagram illustrating waveforms of voltages VRAMP1, VRAMP2, and AND_OUT signal of the conventional relaxation oscillator 100 are shown. The operation of the relaxation oscillator 100 will now be explained with reference to FIG. 1B. At time t0 with switch D2 closed and switch S1 open, charging of the capacitor 112a through the charging resistor 110 is initiated. Further, switch D1 is open and switch S2 is closed. As a result, the capacitor 112b is at ground potential.
The charging of the capacitor 112a causes the voltage at the negative terminal (VRAMP1) of the comparator 116a to begin to increase. Since, the capacitor 112b is at ground potential, the voltage at the negative terminal of the comparator 116b (VRAMP2) remains at ground potential while the voltage VRAMP1 increases. The positive terminals of the comparators 116a and 116b receive a constant voltage generated by the reference voltage generating circuit 104 through the voltage tap T1. The reference voltage generating circuit 104 generates a constant voltage using a resistance ladder made up of the resistors 114a and 114b. In a scenario when the resistors 114a and 114b are identical and a first end of the resistors ladder is connected to the voltage source VDD, that delivers a constant voltage VDD, and a second end connected to ground, then the voltage obtained at the voltage tap T1 is VDD/2. This constant voltage is provided to the positive terminals of the comparators 116a and 116b. 
The comparators 116a and 116b compare the voltages VRAMP1 and VRAMP2, respectively, with the voltage VDD/2 to generate output signals X and Y, respectively. At the beginning of the circuit operation VRAMP1 and VRAMP2 are less than VDD/2; therefore output signals X and Y are high. As a result, the output of the AND gate 118, AND_OUT signal, is also high. The complement of the AND_OUT signal is provided as an input clock signal to the divide-by-2 counter 120. The divide-by-2 counter 120 toggles the states of the output signals, (the ramp voltage switching signals D1′ and D2′), when the input clock signal switches to a low state. Thus, the states of the outputs are stable when VRAMP1 and VRAMP2 are less than VDD/2. As a result, the OSC_OUT signal generated by the oscillator signal generating circuit 108 is also high.
Subsequently, at time t1, VRAMP1 becomes equal to VDD/2 so the output signal X goes low, which in turn causes the AND_OUT signal to go low. This results in the ramp voltage switching signals D1′ and D2′ toggling their respective states. Thus, the ramp voltage switching signal D1′ switches to a high state and the ramp voltage switching signal D2′ switches to a low state. As a result, switches S2 and D2 are opened and switches S1 and D1 are closed. This results in discharging of the capacitor 112a and initiation of charging of the capacitor 112b. As a result, VRAMP1 switches to ground potential and VRAMP2 begins to increase. The output signal X of the comparator 116a momentarily goes low (when VRAMP1 becomes greater than VDD/2), however subsequent to VRAMP1 switching to ground potential, the output signal X goes high. Additionally, since VRAMP2 is less than VDD/2 when the capacitor 112b starts charging, the output signal Y of the comparator 116b is also high. Thus, the AND_OUT signal momentarily goes low, and subsequently switches back to high. As mentioned earlier, the ramp voltage switching signal D1′ changes state when the AND_OUT signal goes low, thus a pulse is obtained in the OSC_OUT signal every time the AND_OUT signal goes low. The above-described sequence of charging and discharging of the capacitors 112a and 112b is repeated resulting in generation of the OSC_OUT signal.
The above system for generation of the OSC_OUT signal involves continual charging and discharging of the RC circuits including Rcharge and C1 and Rcharge and C2. Thus, the frequency of the OSC_OUT signal is controlled by the time required to charge the capacitors 112a and 112b or the time constant of the RC circuit. To increase the frequency of the OSC_OUT signal, the time required for charging the capacitors 112a and 112b must be decreased. To achieve a reduction in the charging time of the capacitors, the charge current used to charge the capacitors must be increased. Thus, the higher the frequency of the OSC_OUT signal, the greater the current consumption. Since, current consumption and frequency are related, a decrease in current consumption translates into a decrease in the frequency of the OSC_OUT signal. It would be advantageous to have a relaxation oscillator that allows for an increase in the frequency of the OSC_OUT signal without increasing current consumption, and thus providing high frequency oscillator signals at low power.